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features ? supply voltage up to 40v r dson typically 0.8 ? at 25c, maximum 1.8 ? at 200c up to 1.0a output current three half-bridge outputs formed by three high-side and three low-side drivers capable of switching loads such as dc moto rs, bulbs, resistors, capacitors, and inductors pwm capability up to 25 khz for each high-side output controlled by external pwm signal no shoot-through current outputs short-circuit protected selective overtemperature protection for each switch and overtemperature prewarning undervoltage protection various diagnostic functions such as sh orted output, open load, overtemperature and power-supply fail detection serial data interface, daisy chain ca pable, up to 2 mhz clock frequency qfn18 package 1. description the ata6832 is a fully protected driver ic specially designed for high temperature applications. in mechatronic solutions, for example turbo charger or exhaust gas recir- culation systems, many flaps have to be c ontrolled by dc motor driver ics which are located very close to the hot engine or actuator where ambient temperatures up to 150c are usual. due to the advantages of soi technology junction temperatures up to 200c are allowed. this enables new co st effective board design possibilities to achieve complex mechatronic solutions. the ata6832 is a triple half-bridge driver to control up to 3 different loads by a micro- controller in automotive and industrial applications. each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 1.0a. due to the enhanced pwm signal (up to 25 khz) it is possible to generate a smooth control of, for example, a dc motor without any noise. the drivers are internally connected to form 3 half-bridges and can be controlled separately from a stand ard serial data interface, enabling all kinds of loads, such as bulbs, resistors, capacitors and inductors, to be combined. the ic design especially supports the appl ication of h-bridges to drive dc motors. protection is guaranteed with respect to sh ort-circuit conditions, overtemperature and undervoltage. various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. automotive qualification (protec- tion against conducted interferences, emc protection and 2-kv esd protection) gives added value and enhanced quality for exacting requirements of automotive applications. high temperature triple half-bridge driver with spi and pwm ata6832 4951c?auto?02/08
2 4951c?auto?02/08 ata6832 figure 1-1. block diagram fault detector fault detector s i h s 2 l s 2 h s 1 l s 1 control logic 5 clk 6 pwm 7 do 3 cs 4 di input register ouput register serial interface h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r h s 3 l s 3 o l d p h 2 p l 2 p h 1 p l 1 p h 3 p l 3 p s f fault detector n. u. n. u. n. u. t p n. u. n. u. n. u. i n h o v l fault detector fault detector power on reset charge pump uv protection thermal protection fault detector vs1 10 vs2 11 vcc 9 gnd 18 gnd 17 gnd 14 gnd 8 out3f 2 out3s 1 out1f 15 out1s 16 out2f 12 out2s 13 o s c
3 4951c?auto?02/08 ata6832 2. pin configuration figure 2-1. pinning qfn24 out3s out3f cs di clk pwm out2f vs2 vs1 vcc gnd do pgnd3 pgnd1 out1s out1f pgnd2 out2s 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 13 14 table 2-1. pin description pin symbol function 1 out3s used only for final testing, to be connected to out3f 2 out3f half-bridge output 3; formed by internally connecting power mos high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 3cs chip select input; 5v cmos logic level input with internal pull-up; low = serial communication is enabled, high = disabled 4di serial data input; 5v cmos logic level input with inte rnal pull-down; receives serial data from the control device; di expects a 16-bit control word with lsb transferred first 5clk serial clock input; 5v cmos logic level input with internal pull-down; controls serial data input interface and internal shift register (f max = 2 mhz) 6 pwm pwm input; 5v cmos logic level input with internal pull-down 7do serial data output; 5v cmos logic-le vel tri-state output for out put (status) register dat a; sends 16-bit status information to the microcontroller (lsb transferred firs t); output will remain tri-stated unless device is selected by cs = low; this allows several ics to operate on only one data-output line 8 gnd ground 9 vcc logic supply voltage (5v) 10 vs1 power supply for output stages out1 and out2; internal supply 11 vs2 power supply for output stages out2 and out3; internal supply 12 out2f half-bridge output 2; formed by inte rnally connected power mos high-side switch 2 and low-side switch 2 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 13 out2s used only for final testing, to be connected to out2f 14 pgnd2 power ground out2 15 out1f half-bridge output 1; formed by inte rnally connected power mos high-side switch 1 and low-side switch 1 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load 16 out1s used only for final testing, to be connected to out1f 17 pgnd1 power ground out1 18 pgnd3 power ground out3
4 4951c?auto?02/08 ata6832 3. functional description 3.1 serial interface data transfer starts with the falling edge of th e cs signal. data must appear at di synchronized to clk and is accepted on the falling edge of the clk signal. the lsb (bit 0, srr) has to be transferred first. execution of new input data is enabled on the rising edge of the cs signal. when cs is high, pin do is in tri-state c ondition. this output is enabled on the falling edge of cs. output data will change their state with the ri sing edge of clk and stay stable until the next rising edge of clk appears. lsb (bit 0, tp) is transferred first. figure 3-1. data transfer srr ls1 hs1 ls2 hs2 ls3 hs3 npl! ph1 pl2 ph2 pl3 ph3 old ocs si cs di clk do tp s1l s1h s2l s2h s3l s3h n. u. n. u. n. u. n. u. n. u. n. u. ovl inh psf 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 table 3-1. input data protocol bit input register function 0srr status register reset (high = reset; the bits psf and ovl in the output data register are set to low) 1 ls1 controls output ls1 (h igh = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 pl1 output ls1 additionally controlled by pwm input 8 ph1 output hs1 additionally controlled by pwm input 9 pl2 see pl1 10 ph2 see ph1 11 pl3 see pl1 12 ph3 see ph1 13 old open load detection (low = on) 14 ocs overcurrent shutdown (high = overcurrent shutdown is active) 15 si software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because the digital part is still powered)
5 4951c?auto?02/08 ata6832 table 3-2. output data protocol bit output (status) register function 0 tp temperature prewarning: high = warning 1 status ls1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detect ed if the corresponding output is switched off); not affected by srr 2 status hs1 normal operation: high = output is on, low = output is off open-load detection: high = open load, low = no open load (correct load condition is detect ed if the corresponding output is switched off); not affected by srr 3 status ls2 description see ls1 4 status hs2 description see hs1 5 status ls3 description see ls1 6 status hs3 description see hs1 7 n. u. not used 8 n. u. not used 9 n. u. not used 10 n. u. not used 11 n. u. not used 12 n. u. not used 13 ovl over-load detected: set high, when at least one output is switched off by a short-circuit condition or an ov ertemperature event. bits 1 to 6 can be used to detect the affected switch 14 inh inhibit: this bit is controlled by software (bit si in input register) high = standby, low = normal operation 15 psf power-supply fail: undervoltage at pin vs detected
6 4951c?auto?02/08 ata6832 after power-on reset, the input register has the following status: the following patterns are used to enable internal test modes of the ic. do not use these pat- terns during normal operation. 3.2 power-supply fail if undervoltage is detected at pin vs, the power-supply fail bit (psf) in the output register is set and all outputs are disabled. to detect an undervoltage, its duration has to last longer than the undervoltage detection delay time t duv . the outputs are enabled immediately when the supply voltage returns to the normal operational value. th e psf bit stays high until it is reset by the srr bit in the input register. 3.3 open-load detection if the open-load detection bit (old) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current i out1-3 ). if the current through the external load does not reach the open-load detection current, the corre- sponding bit of the output in the output register is set to high. switching on an output stage with the old bit set to low disables the open-load function for this output. bit 15 si bit 14 ocs bit 13 old bit 12 ph3 bit 11 pl3 bit 10 ph2 bit 9 pl2 bit 8 ph1 bit 7 pl1 bit 6 hs3 bit 5 ls3 bit 4 hs2 bit 3 ls2 bit 2 hs1 bit 1 ls1 bit 0 srr hhhlllllllllllll bit 15 bit 14 bit 13 (ocs) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) hhhhhlllllllllll hhhllhhlllllllll hhhllllhhlllllll
7 4951c?auto?02/08 ata6832 3.4 overtemperature protection if the junction temperature of one or more output stages exceeds the thermal prewarning thresh- old, t jpw set , the temperature prewarning bit (tp) in the output register is set. when the temperature falls below the thermal prewarning threshold, t jpw reset , the bit tp is reset. the tp bit can be read without transferring a complete 16- bit data word. the status of tp is available at pin do with the falling edge of cs. after the microc ontroller has read this in formation, cs is set high and the data transfer is interrupted without affecting the status of input and output registers. if the junction temperature of an output stage exceeds the thermal shutdown threshold, t jswitch off , the affected output is disabled and the correspondi ng bit in the output register is set to low. addi- tionally, the overload detection bit (ovl) in the output register is set. the output can be enabled again when the temperature falls below the thermal shutdown threshold, t jswitch on , and the srr bit in the input register is set to high. the hyst eresis of thermal prewarning and shutdown thresh- old avoids oscillations. 3.5 short-circuit protection the output currents are limited by a current regulator. overcurrent detection is activated by writ- ing a high to the overcurrent shutdown bit (ocs) bit in the input register. when the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off, fol- lowing a delay time (t dsd ). the over-load detection bit (ovl) is set and the corresponding status bit in the output register is set to low. for ocs = low, the overcurrent shutdown is inactive and the ovl bit is not set by an overcurrent. by writing a high to the srr bit in the input register the ovl bit is reset and the disabled outputs are enabled. 3.6 inhibit the si bit in the input register has to be set to zero to inhibit the ata6832. in this state, all output stages are then turned off but the serial interface remains active. the out- put stages can be reactivated by setting bit si to ?1?. 3.7 pwm mode the common input for all six outputs is pin pwm ( figure 3-2 ). the selection of the outputs, which are controlled by pwm, is done by input data register plx or phx. in addition to the pwm input register, the corresponding input registers hsx and lss have to be set. switching the high side outputs is possible up to 25 khz, low side switches up to 8 khz. figure 3-2. output control by pwm pin outx bit lsx/hsx bit plx/phx pin pwm
8 4951c?auto?02/08 ata6832 4. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters pin symbol value unit supply voltage 10, 11 v vs ?0.3 to +40 v supply voltage t < 0.5s; i s > ?2a 10, 11 v vs ?1 v logic supply voltage 9 v vcc ?0.3 to +7 v logic input voltage 3, 4, 5, 6 v cs , v di , v clk , v pwm ?0.3 to v vcc + 0.3 v logic output voltage 7 v do ?0.3 to v vcc + 0.3 v input current 3, 4, 5, 6 i cs , i di , i clk , i pwm ?10 to +10 ma output current 7 i do ?10 to +10 ma output current 2, 12, 15 i out1 , i out2 , i out3 internally limited, see output specification output voltage 2, 12, 15 i out1 , i out2 , i out3 ?0.3 to +40 v reverse conducting current (t pulse = 150 s) 2, 12, 15 i out1 , i out2 , i out3 17 a junction temperature range t j ?40 to +200 c storage temperature range t stg ?55 to +200 c ambient temperature range t a ?40 to +150 c 5. thermal resistance parameters test conditions symbol value unit thermal resistance from junction to case r thjc 15 k/w thermal resistance from junction to ambient depends on the pc board r thja 40 k/w 6. operating range parameters symbol value unit supply voltage v vs v uv (1) to 40 v logic supply voltage v vcc 4.75 to 5.25 v logic input voltage v cs , v di , v clk , v pwm ?0.3 to v vcc v serial interface clock frequency f clk 2 mhz pwm input frequency f pwm max. 25 khz junction temperature range t j ?40 to +150 c note: 1. threshold for undervoltage description
9 4951c?auto?02/08 ata6832 7. noise and surge immunity parameters test conditions value conducted interferences iso 7637-1 level 4 (1) interference suppression vde 0879 part 2 level 5 esd (human body model) esd s 5.1 2 kv cdm (charge device model) esd stm5.3.1 500v note: 1. test pulse 5: v smax = 40v 8. electrical characteristics 7.5v < v s < 40v; 4.75v < v cc < 5.25v; inh = high; ?40c t j 200c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 current consumption 1.1 quiescent current vs v vs < 20v, si = low 10, 11 i vs 160 aa 1.2 quiescent current vcc 4.75v < v vcc < 5.25v, si = low 9i vcc 60 160 a a 1.3 supply current vs v vs < 20v normal operating, all outputs off, input register bit 13 (old) = high 10, 11 i vs 46maa 1.4 supply current vcc 4.75v < v vcc < 5.25v, normal operating 9i vcc 350 650 a a 1.5 discharge current vs v vs = 32.5v, inh = low 10, 11 i vs 0.5 5.5 ma a 1.6 discharge current vs v vs = 40v, inh = low 10, 11 i vs 2.0 14 ma a 2 undervoltage detection, power-on reset 2.1 power-on reset threshold 9v vcc 3.1 3.9 4.5 v a 2.2 power-on reset delay time after switching on v cc t dpor 30 95 190 s a 2.3 undervoltage-detection threshold v cc =5v 10, 11 v uv 5.5 7.1 v a 2.4 undervoltage-detection hysteresis v cc = 5v 10, 11 ? v uv 0.6 v a 2.5 undervoltage-detection delay time t duv 10 40 s a 3 thermal prewarning and shutdown 3.1 thermal prewarning set t jpw set 170 195 220 c b 3.2 thermal prewarning reset t jpw reset 155 180 205 c b 3.3 thermal prewarning hysteresis ? t jpw 15 k b 3.4 thermal shutdown off t j switch off 200 225 250 c b *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and swit ch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
10 4951c?auto?02/08 ata6832 3.5 thermal shutdown on t j switch on 185 210 235 c b 3.6 thermal shutdown hysteresis ? t j switch off 15 k b 3.7 ratio thermal shutdown off/thermal prewarning set t j switch off/ t jpw set 1.05 1.2 b 3.8 ratio thermal shutdown on/thermal prewarning reset t j switch on/ t jpw reset 1.05 1.2 b 4 output specification (out1 to out3) 4.1 on resistance i out 1-3 = ?0.9 a 2, 12, 15 r dson1-3h 1.8 ? a 4.2 i out 1-3 = ?0.9 a 2, 12, 15 r dson1-3l 1.8 ? a 4.3 high-side output leakage current v out 1-3 h = 0v , output stages off 2, 12, 15 i out1-3h ?60 a a 4.4 low-side output leakage current v out 1-3 l = v vs, output stages off 2, 12, 15 i out1-3l 300 a a 4.5 high-side switch reverse diode forward voltage i out = 1.5a 2, 12, 15 v out1-3 ? v vs 2va 4.6 low-side switch reverse diode forward voltage i out 1-3 l = ?1.5a 2, 12, 15 v out1-3l 2va 4.7 high-side overcurrent limitation and shutdown threshold 7.5v < v vs < 20v 2, 12, 15 i out1-3 1.0 1.3 1.7 a a 4.8 low-side overcurrent limitation and shutdown threshold 7.5v < v vs < 20v 2, 12, 15 i out1-3 ?1.7 ?1.3 ?1.0 a a 4.9 high-side overcurrent limitation and shutdown threshold 20v < v vs < 40v 2, 12, 15 i out1-3 1.0 1.3 2.0 a a 4.10 low-side overcurrent limitation and shutdown threshold 20v < v vs < 40v 2, 12, 15 i out1-3 ?2.0 ?1.3 ?1.0 a a 4.11 overcurrent shutdown delay time t dsd 10 40 s a 4.12 high-side open load detection current input register bit 13 (old) = low, output off v vs = 13v 2, 12, 15 i out1-3h ?12 ?5 ma a 8. electrical characteristics (continued) 7.5v < v s < 40v; 4.75v < v cc < 5.25v; inh = high; ?40c t j 200c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and swit ch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
11 4951c?auto?02/08 ata6832 4.13 low-side open load detection current input register bit 13 (old) = low, output off v vs = 13v 2, 12, 15 i out1-3l 0.05 1.4 ma a 4.14 open load detection current ratio iol outlx / iol outhx 1.2 3 4.15 high-side output switch on delay (1),(2) v vs = 13v r load =30 ? t don 20 s a 4.16 low-side output switch on delay (1),(2) v vs = 13v r load =30 ? t don 20 s a 4.17 high-side output switch off delay (1),(2) v vs =13v r load = 30 ? t doff 20 s a 4.18 low-side output switch off delay (1),(2) v vs =13v r load = 30 ? t doff 3 sa 4.19 dead time between corresponding high-side and low-side switches v vs =13v r load = 30 ? t don ? t doff 1 sa 4.20 ? t dpwm low-side switch (3) v vs = 13v r load = 30 ? ? t dpwm = t don ? t doff 20 s a 4.21 ? t dpwm high-side switch (3) v vs = 13v r load = 30 ? ? t dpwm = t don ? t doff ?5 5 s a 5 logic inputs di, clk, cs, pwm 5.1 input voltage low-level threshold 3, 4, 5, 6 v il 0.3 v vcc va 5.2 input voltage high-level threshold 3, 4, 5, 6 v ih 0.7 v vcc va 5.3 hysteresis of input voltage 3, 4, 5, 6 ? v i 50 700 mv a 5.4 pull-down current pins di, clk, pwm v di , v clk, v pwm = v cc 4, 5, 6 i pd 570 aa 5.5 pull-up current pin cs v cs = 0v 3 i pu ?70 ?5 a a 6 serial interface ? logic output do 6.1 output-voltage low level i dol = 2 ma 7 v dol 0.4 v a 6.2 output-voltage high level i dol = ?2 ma 7 v doh v vcc ? 0.7v va 8. electrical characteristics (continued) 7.5v < v s < 40v; 4.75v < v cc < 5.25v; inh = high; ?40c t j 200c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and swit ch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode.
12 4951c?auto?02/08 ata6832 6.3 leakage current (tri-state) v cs = v cc 0v < v do < v vcc 7i do ?15 +15 a a 7 inhibit input ? timing 7.1 delay time from standby to normal operation t dinh 100 s a 8. electrical characteristics (continued) 7.5v < v s < 40v; 4.75v < v cc < 5.25v; inh = high; ?40c t j 200c; t a 150c; unless otherwise specified, all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter notes: 1. delay time between rising edge of input signal at pin cs after data transmission and swit ch on/off output stages to 90% of final level. device not in standby for t > 1 ms. 2. delay time between rising/falling edge of input signal at pin pwm and switch on/off output stages to 90% of final level. 3. difference between switch-on and switch-off delay time of input signal at pin pwm to output stages in pwm mode. 9. serial interface timing no. parameters test condit ions pin timing chart no. (1) symbol min. typ. max. unit type* 8 serial interface timing 8.1 do enable after cs falling edge c do = 100 pf 7 1 t endo 200 ns d 8.2 do disable after cs rising edge c do = 100 pf 7 2 t disdo 200 ns d 8.3 do fall time c do = 100 pf 7 - t dof 100 ns d 8.4 do rise time c do = 100 pf 7 - t dor 100 ns d 8.5 do valid time c do = 100 pf 7 10 t doval 200 ns d 8.6 cs setup time 3 4 t cssethl 225 ns d 8.7 cs setup time 3 8 t cssetlh 225 ns d 8.8 cs high time 3 9 t csh 500 ns d 8.9 clk high time 5 5 t clkh 225 ns d 8.10 clk low time 5 6 t clkl 225 ns d 8.11 clk period time 5 - t clkp 500 ns d 8.12 clk setup time 5 7 t clksethl 225 ns d 8.13 clk setup time 5 3 t clksetlh 225 ns d 8.14 di setup time 4 11 t diset 40 ns d 8.15 di hold time 4 12 t dihold 40 ns d *) type means: a =100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
13 4951c?auto?02/08 ata6832 figure 9-1. serial interface timing with chart number 1 do cs clk cs do clk output do: high level = 0.8 v cc , low level = 0.2 v cc inputs di, clk, cs: high level = 0.7 v cc , low level = 0.3 v cc di 11 5 6 8 10 12 3 9 2 4 7
14 4951c?auto?02/08 ata6832 10. application circuit figure 10-1. application circuit 10.1 application notes connect the blocking capacitors at v cc and v s as close as possible to the power supply and gnd pins. recommended value for capacitors at v s : ? electrolytic capacitor c > 22 f in para llel with a ceramic capacitor c = 100 nf. the value for the electrolytic capacitor depends on external loads, conducted interferences, and the reverse conducting current i out1,2,3 . recommended value for capacitors at v cc : ? electrolytic capacitor c > 10 f in parallel with a ceramic capacitor c = 100 nf. to reduce thermal resistance, place cooling ar eas on the pcb as close as possible to the gnd pins and to the die pad. fault detector fault detector s i h s 2 l s 2 h s 1 l s 1 control logic 5 clk 6 pwm 7 do 3 cs 4 di input register ouput register serial interface h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 s r r h s 3 l s 3 o l d p h 2 p l 2 p h 1 p l 1 p h 3 p l 3 p s f fault detector n. u. n. u. n. u. t p n. u. n. u. n. u. i n h o v l fault detector fault detector power on reset charge pump uv protection thermal protection fault detector vs1 10 vs2 11 vcc 9 gnd 18 gnd 17 gnd 14 gnd 8 out3f 2 out1f 15 out2f 12 o s c v cc v cc u5021m watchdog reset trigger micro- controller m m 1 v cc + v s 13v v batt 5v v cc byv28 + 13 16
15 4951c?auto?02/08 ata6832 12. package information 13. revision history 11. ordering information extended type number package remarks ata6832-piqw qfn18, 4 mm 4 mm taped and reeled, pb-free specifications according to din technical drawings 0.4 0.1 18 1 6 pin 1 identification 13 18 12 7 1 6 package: vqfn_4 x 4_18l exposed pad 2.7 x 3.175 dimensions in mm not indicated tolerances 0.05 issue: 1; 26.04.07 drawing-no.: 6.543-5133.01-4 0.2 2.5 0.175 0.5 nom. z 2.5 2.7 0.15 3.175 0.15 z 10:1 0.9 0.1 0.23 0.07 4 top bottom please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4951c-auto-02/08 ? section 4 ?absolute maximum ratings? on page 8 changed 4951b-auto-06/07 ? put datasheet in the newest template ? package drawing changed ? block diagram changed ? pin description changed ? el. char. table: rows 1.6, 4.12, 4.13 and 4.21 changed ? application circuit drawing changed
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